vhdl源程序 全加器,四位全加器设计VHDL

这是一个通用的全加器，b: instd _ logic _ vector (15下降到0)；s:out STD _ logic _ vector(15 down to 0)；cout:out STD _ logic)；endadder16barchitecturebehavofadder 16 bis signals int:STD _ logic _ vector(16 down to 0)；信号a。

library IEEE；use IEEE . STD _ logic _ 1164 . all；use IEEE . STD _ logic _ arith . all；use IEEE . STD _ logic _ unsigned . all；entityader 16 bisport(CIN:instd _ logic；a，b:instd _ logic _ vector(15 down to 0)；s:out STD _ logic _ vector(15 down to 0)；cout:out STD _ logic)；endadder16barchitecturebehavofadder 16 bis signals int:STD _ logic _ vector(16 down to 0)；信号a，

library IEEE；use IEEE . STD _ logic _ 1164 . all；use IEEE . STD _ logic _ unsigned . all；entityquangachi _ 2 weilsport(a，b:instd _ logic _ vector(1 downto 0)；CIN:INSTD _ LOGIC；COUNT:out STD _ LOGIC _ VECTOR(1 downto 0)；C0:OUTSTD _ LOGIC)；ENDQUANJIAQI _ 2WEIarchitecturevhdlofquangaqi _ 2 weiissignal q _ TEMP:STD _ LOGIC _ VECTOR(2 downto 0)；开始温。